Case Study 4 : Timing Generator PLL for High Resolution Digital Cameras

Brief Description of the Project requirement:

The customer wanted ELVEEGO to design a PLL for Timing Generator used in a High Resolution Camera. This PLL is supplied with a reference frequency of 54MHz from a Crystal or an FPGA and will output selectable frequency options of 108MHz, 54MHz (through mode), 27MHz and 13.5MHz.

Challenges:

The primary challenge in this project was that the available schedule was only 2.5 months for the complete design from Specifications through GDS delivery. Also, there was an additional requirement from the customer towards the end of the project to incorporate real time switching of the PLL outputs between 108MHz, 54MHz, 27MHz and 13.5MHz.

Solutions and Project Execution Summary:

This PLL was designed in UMC 110nm Image Sensor Process with a typical Power Supply voltage of 1.5V. Many of the sub-blocks of this PLL was designed in parallel and also more simulators were used in this project with lots of simulation automations to complete the design and verification of this PLL within a very short time. This PLL has on-chip loop filter and incorporates loop parameter tuning options.

Towards the closing stage of the project, the additional requirement of real time PLL output switching was incorporated without any change in the PLL design as such. The PLL macro layout was done using upto Metal 4.

This PLL was designed within a maximum current consumption of less than 3.2mA. The project was executed within a schedule of 2.5 months for the complete schematic design through layout, simulation verifications and GDS delivery.

Present Status

The design has been delivered successfully to the customer and the end customer is using this PLL in its Timing Generator chip.