Case Study 3 : Fractional PLL for Short length Wireless Communication FSK Transceiver

Brief Description of the Project requirement:

The customer wanted ELVEEGO to design a PLL with the option of Integer mode and Fractional mode selection to be used as a local oscillator in an FSK Transceiver for short length Wireless Communication applications. The requirement also had various programmability options for Charge Pump Current, VCO Gain etc., for selectable reference frequency and related loop parameter fine tuning. The design target was to get output frequency of 9.8MHz to 14.1MHz range with fractional frequency deviation of less than +/-50KHz using reference frequency options of 18MHz/19.2MHz/26MHz/38.4MHz. The PLL provides I and Q channel differential signal outputs to be used in the Transceiver.

Challenges:

The design was to be performed from scratch using the Analog Custom design flow even for the Sigma Delta Modulator of Fractional Divider. The design targeted a very low power consumption specification. Simulation time was also one big challenge in this project as the fractional mode of the PLL requires long simulation time.

Solutions and Project Execution Summary:

The design of this project was performed in TSMC 180nm process with 1.8V typical Power Supply. The PLL and Sigma Delta Modulator sub-blocks were modelled using Verilog-A to develop a suitable architecture and architecture details like modulator order and other parameters like number of bits for the fractional divider, PLL loop parameters like CP current, VCO Gain, Loop Filter etc.,. Then the project was progressed to actual schematic design using the Cadence custom Analog design flow. The digital logic gates used in the Sigma Delta Modulator and other parts of the PLL were designed custom because one of the primary requirement was to have very low power consumption. So, each of the logic gates were customised for its usage.

It was not possible to perform top level PLL simulations in all PVT conditions due to long simulation time required for the PLL in integer and fractional modes. Based on past design experience, design verification conditions were selected to reduce the number of verification conditions while considering to cover all extreme conditions for Process, Voltage and temperature variations.

The PLL was designed with a total current consumption of less than 2.5mA in the fractional mode.

This project was executed within a time frame of around 3.5 months for the complete schematic design through layout, simulation verifications and GDS delivery.

Present Status

The customer has successfully taped out the FSK Transceiver and it is working successfully in Silicon and is being used in the end customer’s products.